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	<title>WG211/M11Scholz - Revision history</title>
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	<entry>
		<id>http://mw.hh.se/wg211/index.php?title=WG211/M11Scholz&amp;diff=677&amp;oldid=prev</id>
		<title>Ups: Created page with &quot;&#039;&#039;&#039;Effective Parallel Code Generation Through Auto-Sequentialisation&#039;&#039;&#039; by Sven-Bodo Scholz  Creating parallel programs that make effective use of a range of parallel architectur...&quot;</title>
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		<updated>2012-06-20T11:00:40Z</updated>

		<summary type="html">&lt;p&gt;Created page with &amp;quot;&amp;#039;&amp;#039;&amp;#039;Effective Parallel Code Generation Through Auto-Sequentialisation&amp;#039;&amp;#039;&amp;#039; by Sven-Bodo Scholz  Creating parallel programs that make effective use of a range of parallel architectur...&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;&amp;#039;&amp;#039;&amp;#039;Effective Parallel Code Generation Through Auto-Sequentialisation&amp;#039;&amp;#039;&amp;#039; by Sven-Bodo Scholz&lt;br /&gt;
&lt;br /&gt;
Creating parallel programs that make effective use of a range of parallel&lt;br /&gt;
architectures is hard. Even when a given algorithm offers a lot of&lt;br /&gt;
potential parallelism it is a challenge to identify which of these options&lt;br /&gt;
for parallelisation are the most suitable ones for a given target&lt;br /&gt;
architecture. In fact, it turns out that these choices are architecture&lt;br /&gt;
dependent. &lt;br /&gt;
&lt;br /&gt;
Aiming for programmer productivity in a world of changing hardware options&lt;br /&gt;
we argue in favour of a generative approach: We suggest to start out from&lt;br /&gt;
rather abstract program specifications that expose as much potential&lt;br /&gt;
parallelism as possible. Such specification then can be used as input for a&lt;br /&gt;
program generator that produces parallel codes optimised for the particular&lt;br /&gt;
needs of a given hardware architecture. &lt;br /&gt;
&lt;br /&gt;
In this talk, we briefly present the various challenges we have met when&lt;br /&gt;
generating parallel programs from the functional, data-parallel programming&lt;br /&gt;
language SaC. In particular we highlight the differences in our &lt;br /&gt;
observations when looking at a range of architectures as targets: SMPs,&lt;br /&gt;
GPUs, and experimental manycore architectures.  We close with a first look&lt;br /&gt;
at the challenges when looking at FPGAs as accelerators.&lt;/div&gt;</summary>
		<author><name>Ups</name></author>
	</entry>
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