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Created page with "The linear-time simulation of 2-way deterministic pushdown automata (2DPDA) is revisited. Following the semantics-based approach by Jones, a recursive interpreter is given which,..."
 
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The linear-time simulation of 2-way deterministic pushdown automata (2DPDA) is revisited. Following the semantics-based approach by Jones, a recursive interpreter is given which, when extended with random-access memory, performs a linear-time simulation of 2DPDA. The simulation is then extended to non-deterministic pushdown automata yielding a polynomial-time simulator. The constructions may provide an alternative angle to assess some program generation and complexity problems.
''Automatic Generation of an Electronics-to-Middleware Interface Layer'' by Ulrik Pagh Schultz, joint work with Anders Lange
 
This talk reports on a work-in-progress, the development of a DSL for
automatically generating VHDL and high-level code for using FPGAs to
interface electronics (sensors and actuators) to high-level
middleware.  All real-time control is handled in the FPGA, and the
approach allows software components to be easily migrated from
high-level middleware to a real-time context executing on the FPGA.
This talk presents the overall idea, with a focus on current
considerations on design and implementation related to program
generation.

Latest revision as of 14:53, 28 May 2013

Automatic Generation of an Electronics-to-Middleware Interface Layer by Ulrik Pagh Schultz, joint work with Anders Lange

This talk reports on a work-in-progress, the development of a DSL for automatically generating VHDL and high-level code for using FPGAs to interface electronics (sensors and actuators) to high-level middleware. All real-time control is handled in the FPGA, and the approach allows software components to be easily migrated from high-level middleware to a real-time context executing on the FPGA. This talk presents the overall idea, with a focus on current considerations on design and implementation related to program generation.